Intel Xeon Phi announcement and summary

Intel had announced Xeon Phi branding and basic architecture long ago, but we finally have details and pricing. Xeon Phi is essentially a 62-core x86 chip. Different SKUs will have different number of cores and clock speeds enabled. TDPs and rough performance numbers look competitive with offerings such as Nvidia Tesla, but the Xeon Phi offers higher programmability and potentially better efficiency on some workloads. The chip will sit in a PCIe board and can either be used to offload parts of your program, or run the whole program. The board offers a number of programming interfaces such as OpenMP that are a lot more convenient than writing say CUDA code. Compared to GPUs, it should be relatively easy to get your application up-and-running on a Xeon Phi though optimization will still require some effort.

However, I am still happy to report that OpenCL is still fully supported, so porting code from GPUs to Xeon Phi is still easy.  Kudos to Intel for getting behind OpenCL and actually delivering fully working products.

Each core has an in-order dual-issue x86 core with SMT (4 threads) backed by a 512-bit vector unit capable of doing FMA operations. Each vector unit can do 8 fp64 FMAs (16 flops) or 16 fp32 FMAs (32 flops) each cycle. While there is no SSE or AVX available on this core, the vector instruction set is actually very nice with operations like scatter-gather as well as per-lane write masks. IMO it is a cleaner and more flexible vector ISA than say AVX.
Unlike GPUs, Xeon Phi does not have an on-chip user-programmable local memory. Instead, it is backed by a large 512kB L2 cache on each core and the cache is fully coherent. In total, on a 60-core variant that is 30MB of coherent L2 cache compared to 1-2 MB L2 caches we are used to seeing on GPUs. This is a HUGE win compared to GPUs IMO and should give very good efficiency on some workloads such as some types of sparse matrices. Honestly, dealing with on-chip shared memory on GPUs is a giant pain.

My rough guess is that Nvidia’s Tesla K20X will retain a 10-15% edge in some brute force tests as well as tests like generic dense linear algebra, and will retain an advantage in fp32 workloads, but there will also be workloads where Xeon Phi will win out. And overall Xeon Phi should retain a programmability advantage.

As an academic (currently), I am a little disappointed that I will likely not be able to test my tools on a Xeon Phi as we do not have the budget to buy them. With Nvidia, one can start experimenting with CUDA by buying just a $100 card and Nvidia has also been open about seeding their boards to universities where they feel appropriate. Xeon Phis start upwards of $2k (much like Teslas) so not many labs will have access to them. Would like to see Intel offer some kind of program to univs to boost the Xeon Phi’s popularity to increase the base of programmer pool available for their card 🙂

Overall, a very good showing from Intel, though they do need to keep executing as other competitors are not sitting idle either.

Intel Xeon Phi and OpenCL

Does the Intel Xeon Phi support OpenCL? It has been hard to get a definitive official answer, but all the signs point to “yes”.

Take this story on HPCWire about Accelereyes adding Xeon Phi support to their well-known ArrayFire library through OpenCL. Then there is Intel’s marketing material PDF showing OpenCL as an example of languages that run on the Xeon Phi. There was also an interview of Yariv Aridor of Intel, who was described as leading the implementation of OpenCL on Xeon Phi.

Intel already has a x86 implementation for their Core processors. So, at least for basic support, getting it working on Xeon Phi requires two things. First, they need to add support in the runtime to support the OpenCL APIs such as allocating memory etc. Second, they need to add support in the kernel compiler for the new 512-bit vector instructions in the Xeon Phi instead of AVX on Core processors. Both are certainly doable and does not require a big investment from Intel so there is not much reason for them to not support OpenCL. After all, Intel has traditionally been very good at supporting as many languages on their platform as they can.

I would say, we are definitely going to see OpenCL on Xeon Phi, which is very good news for the OpenCL ecosystem.

Arndale board with Exynos 5250 does NOT do OpenCL right now

Yet another Exynos 5250 device, and still no OpenCL implementation available.
Arndale Board marketing material does mention OpenCL at a few places, but it does not ship with the driver. Source: This forum post. It is frustrating that many vendors in the ARM space keep mentioning OpenCL in their marketing and yet don’t ship working drivers.

Update: In a tweet from @ARMMultimedia, they confirmed that they will make OpenCL BSPs available by the time the board ships. Still waiting for more information about which OS this is for, and whether it will require any NDAs etc. Hopefully we will know soon.

RaijinCL : Autotuning GEMM routines for OpenCL

Announcing a new project: RaijinCL. It is a numerical library for matrix computations for OpenCL though currently only one part is available. The first available part are autotuning GEMM (general matrix multiply) routines. It is a work in progress, and things will improve over time. Do give your feedback.

More information can be found here: http://www.raiijincl.org

Cortex A15 and ARM Mali T604 are here

The new Chromebooks are apparently based upon the Exynos 5250, making them perhaps the first shipping consumer devices with Cortex A15 as well as the ARM Mali T604. ARM Mali T604 theoretically supports OpenCL, which had me excited, but the fly in the ointment is the Chrome OS. Google has confirmed in a forum post that currently there does not exist a way to access OpenCL in Chrome OS and they are not ready to comment upon whether this will change in the future either. This is frankly ridiculous. What’s the point of shipping powerful new hardware when developers are not given access to it? I hope one can load a proper Linux distro like Debian or Ubuntu etc., and hopefully the binary GPU drivers with OpenGL and OpenCL support will be made available for them.

An overview of OpenCL SPIR

(Updated: Corrected NVVM description at 0845 EST on 7th oct)

OpenCL SPIR is a proposed portable binary distribution format for OpenCL programs. The idea is simple. Today, OpenCL kernels are distributed as source strings with the application binary. The source string is then compiled on the user’s machine into native binaries using the OpenCL driver present on the user’s machine. However, this is not always ideal. First, some people would prefer not to distribute their OpenCL kernel sources with their application binaries. Second, there may be more compilation overhead on the user’s machine. Third, compilers for higher-level languages may want to generate GPU code and may want a lower-level and stable target instead of OpenCL C.

In contrast to the situation with OpenCL, consider DirectCompute shaders. The developer writes an awesome shader on his/her machine. The shader can be compiled into a lower-level bytecode format (that is not dependent upon the hardware vendor) and then the bytecode is distributed with the application binary. The bytecode is compiled into binary code by the driver on the user’s computer.

OpenCL SPIR is trying to define a similar portable “binary” distribution format. However, instead of designing their own bytecode from scratch, SPIR is based upon the LLVM IR. Most OpenCL implementations already use some proprietary fork of LLVM IR already thus it was the logical starting point. That is not to say the problem is easy. OpenCL SPIR is meant to be portable, whereas LLVM IR was not really meant to be a portable distribution format. LLVM IR was meant as a compiler IR. There is also some discussion about whether SPIR specification is robust enough that SPIR-to-SPIR compilers/optimizers can be safely written, or whether SPIR is suitable as a target for compilers for languages other than OpenCL C kernel language. The initial goal appears to be to ensure that SPIR is a suitable target for OpenCL C implementations first and not worry about the other use cases.

It is also important to note what OpenCL SPIR is *not*. OpenCL SPIR is not a piece of software. It is simply a specification for a program representation format that vendors are free to implement anyway they choose. There is a lot of wrong reporting on OpenCL SPIR because people seem to confuse LLVM IR with LLVM-the-software. There may end up being a reference OpenCL C to SPIR compiler implementation, and then SPIR-to-binary compilers for supported LLVM backends, but that is *NOT* what is being proposed right now. And even if reference implementations are made available, vendors are free to ignore them.

I will repeat once again. OpenCL SPIR is *not* a piece of software. OpenCL SPIR is simply a distribution format, based upon LLVM IR. Let us consider you are writing a Python to OpenCL compiler. Today, you would be generating OpenCL C. However, in the future, you may want to generate SPIR instead though the initial design is not really meant for this use case. Now integrating SPIR is quite different from a toolchain perspective than integrating LLVM-the-software for CPU code generation that you might use today. Most compilers that use LLVM today for CPUs do not generate LLVM bytecode directly. Instead, LLVM-the-software uses an internal in-memory data structure representation of the LLVM IR with really nice C++ APIs for building these data structures. OpenCL SPIR specification does *NOT* contain this data-structure representation or associated APIs currently. You may get these once there is a reference implementation, but right now, there isn’t.

Comparisons are being made with Nvidia’s NVVM for CUDA. There is a BIG difference, and the difference is that NVVM’s design and implementation goals are quite different than SPIR. Nvidia already has a bytecode format for distributing programs called PTX. NVVM is simply a higher-level layer and there are two pieces to NVVM: NVVM IR and libNVVM. NVVM IR is also an LLVM-based IR, but essentially a clean subset of LLVM instead of being a modification. NVVM IR is not really meant for distribution however, and is meant mostly as a compiler target. Second piece is libNVVM library that generates PTX from NVVM. libNVVM is built using LLVM-the-software and the intended audience is exclusively third-party compiler writers. libNVVM is simply a C++ library based upon LLVM that enables compiler writers (such as compilers for Python to CUDA) to easily generate PTX.

The nice thing about NVVM IR is that it is essentially a subset of the standard LLVM IR. Compiler writers can either generate NVVM IR bytecode directly, or use the LLVM C++ data-structure APIs to generate and manipulate NVVM. I would say the data structure APIs are a lot easier to use. The difference from SPIR is that the LLVM based tooling is available *today* (in RC form, but you get the idea). Many compiler writers are already familiar with LLVM APIs thus making it easy to integrate. Generating libNVVM makes it simpler to target CUDA than the earlier option of generating PTX. For example, with libNVVM you no longer need to worry about low-level stuff like register allocation since that can be taken care of by NVVM.

(edit: To clarify, such tooling should become available in the future for OpenCL SPIR but it is not part of the proposal as it stands today.)

Overall, OpenCL SPIR is a really nice proposal but it is not the solution to all problems that people seem to think it is. Specifically, compiler tooling side from the perspective of a third-party compiler is not very clear right now and I would say Nvidia is ahead on this front in terms of having a integrated stack already almost in-place. However, the potential is clearly there and OpenCL is clearly ahead of APIs (other than CUDA and HSA, see below) in this regard. For example, I have simply failed to get any information from Google about the LLVM-based distribution format they use for Renderscript for Android. DirectCompute defines a binary distribution format, but it does not look like it was designed with third-party compiler writers in mind. There is no tooling support to generate this nor very well-defined easy-to-read documentation, with documentation suggesting that it is mostly an implementation detail that you should not bother about.

I should also mention HSAIL. I would say, from the point of view a third-party compiler writer, HSAIL is the most exciting and well-designed target that I have seen so far based upon the details I have seen. I do hope that HSA foundation puts effort into making the library and tooling side nice as well. I am much more excited about HSAIL than OpenCL SPIR. OpenCL SPIR may very well end up being a stop-gap fix from the perspective of a third-party compiler writer. However, SPIR is still an important and useful step, both for vendors implementing OpenCL, as well as for application writers who are more comfortable in terms of distributing bytecode rather than source strings.